rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9621* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 connection diagram 1 2 3 4 8 7 6 5 ad9621 nc # ?nput +input ? s nc # +v s output nc # optional capacitor cb connected here decreases settling time features 350 mhz small signal bandwidth 130 mhz large signal bw (4 v p-p) high slew rate: 1200 v/ m s fast settling: 11 ns to 0.01%/7 ns to 0.1% 6 3 v supply operation applications adc input driver differential amplifiers if/rf amplifiers pulse amplifiers professional video dac current-to-voltage baseband and video communications pin diode receivers active filters/lntegrators/log amps general description the ad9621 is one of a family of very high speed and wide bandwidth amplifiers utilizing a voltage feedback architecture. these amplifiers define a new level of performance for voltage feedback amplifiers, especially in the categories of large signal bandwidth, slew rate, settling, and low noise. proprietary design architectures have resulted in an amplifier family that combines the most attractive attributes of both cur- rent feedback and voltage feedback amplifiers. the ad9621 ex- hibits extraordinarily accurate and fast pulse response characteristics (7 ns settling to 0.1%) as well as extremely wide small and large signal bandwidth previously found only in cur- rent feedback amplifiers. when combined with balanced high impedance inputs and low input noise current more common to voltage feedback architectures, the ad9621 offers performance not previously available in a monolithic operational amplifier. *protected by u.s. patent 5,150,074 and others pending. other members of the ad962x amplifier family are the ad9622 (g = +2), AD9623 (g = +4), and the ad9624 (g = +6). a separate data sheet is available from analog de- vices for each model. each generic device has been designed for a different minimum stable gain setting, allowing users flexibility in optimizing system performance. dynamic performance speci- fications such as slew rate, settling time, and distortion vary from model to model. the table below summarizes key perfor- mance attributes for the ad962x family and can be used as a selection guide. the ad9621 is offered in industrial and military temperature ranges. industrial versions are available in plastic dip, soic, and cerdip; mil versions are packaged in cerdips. product highlights 1. wide large signal bandwidth 2. high slew rate 3. fast settling 4. output short-circuit protected parameter ad9621 ad9622 AD9623 ad9624 units minimum stable gain +1 +2 +4 +6 v/v harmonic distortion (20 mhz) C52 C66 C64 C66 db large signal bandwidth (4 v p-p) 130 160 190 200 mhz ssbw (0.5 v p-p) 350 220 270 300 mhz slew rate 1200 1500 2100 2200 v/ m s rise/fall time (0.5 v step) 2.4 1.7 1.6 1.5 ns settling time (to 0.1%/0.01%) 7/11 8/14 8/14 8/14 ns input noise (0.1 mhz C 200 mhz) 80 49 36 32 m v rms wideband voltage feedback amplifier
ad9621Cspecifications dc electrical characteristics test ad9621an/aq/ar ad9621sq parameter conditions temp level min typ max min typ max units dc specifications 1 input offset voltage +25 c i C12 2 +12 C12 2 +12 mv full vi C15 +15 C15 +15 mv input bias current +25 ci 7 16 7 16 m a full vi C20 +20 C20 +20 m a input bias current tc full v 35 35 na/ c input offset current +25 c i C2.0 0.3 +2.0 C2.0 +2.0 m a full vi C3.0 +3.0 C3.0 +3.0 m a offset current tc full v 2.5 2.5 na/ c input resistance +25 c v 500 500 k w input capacitance +25 c v 1.2 1.2 pf common-mode range full vi 3.0 3.4 3.0 3.4 v common-mode rejection ratio d v cm = 1 v +25 c i 46 49 46 49 db open loop gain v out = 2 v p-p +25 c v 56 56 db output voltage range full vi 3.0 3.4 3.0 3.4 v output current full vi 60 70 60 70 ma output resistance +25 c v 0.3 0.3 w frequency domain bandwidth (C3 db) small signal v out 0.4 v p-p full ii 230 350 230 350 mhz large signal v out 4.0 v p-p full v 130 130 mhz amplitude of peaking full spectrum full ii 0.1 1.2 0.1 1.2 db amplitude of roll-off 100 mhz full ii 0 0.6 0 0.6 db phase nonlinearity dc to 100 mhz +25 c v 1.1 1.1 degree 2nd harmonic distortion 2 v p-p; 20 mhz full ii C55 C44 C55 C44 dbc 3rd harmonic distortion 2 v p-p; 20 mhz full ii C52 C43 C52 C43 dbc common-mode rejection mode @ 20 mhz +25 c v +28 +28 db spectral input noise voltage 1 to 200 mhz +25 c v 5.6 5.6 nv/ ? hz spectral input noise current 1 to 200 mhz +25 c v 3.6 3.6 pa/ ? hz average equivalent integrated input noise voltage 0.1 to 200 mhz +25 c v 80 80 m v rms time domain slew rate v out = 5 v step full iv 850 1200 850 1200 v/ m s rise/fall time v out = 0.5 v step +25 c v 2.4 2.4 ns v out = 5 v step full iv 4.8 7 4.8 7 ns overshoot v out = 2 v step full iv 0 15 0 15 % settling time to 0.1% v out = 2 v step +25 cv 7 7 ns to 0.01% v out = 2 v step full iv 11 15 11 15 ns to 0.1% 2 v out = 4 v step +25 cv 9 9 ns t0 0.01 2 v out = 4 v step +25 c v 13 13 ns overdrive recovery 1.5x to 2 mv +25 c v 50 50 ns differential gain (4.3 mhz) r l = 150 w +25 c v 0.01 0.01 % differential phase (4.3 mhz) r l = 150 w +25 c v <0.01 <0.01 degree power supply requirements 1 supply voltage ( v s ) full iv 3.0 5.0 5.5 3.0 5.0 5.5 v quiescent current +i s +v s = +5 v full vi 23 29 23 29 ma Ci s Cv s = C5 v full vi 23 29 23 29 ma power supply rejection ratio d v s = 0.5 v +25 c i 54 66 54 66 db notes 1 measured at a v = 21. 2 measured with a 0.001 m f c b capacitor connected across pins 1 and 8. specifications subject to change without notice. rev. 0 C2C ( 6 v s = 6 5 v, r load = 100 w ; a v = 1, unless otherwise noted)
ad9621 rev. 0 C3C absolute maximum ratings 1 supply voltages ( v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v common-mode input voltage . . . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v continuous output current 2 . . . . . . . . . . . . . . . . . . . . . 90 ma operating temperature ranges an, aq, ar . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c sq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +125 c junction temperature ceramic 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 c plastic 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 c lead soldering temperature (1 minute) 4 . . . . . . . . . . +220 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 output is short-circuit protected; for maximum reliability, 90 ma continuous current should not be exceeded. 3 typical thermal impedances (part soldered onto board; no air flow): ceramic dip: q ja = 100 c/w; q jc = 30 c/w plastic soic: q ja = 125 c/w; q jc = 45 c/w plastic dip: q ja = 90 c/w; q jc = 45 c/w 4 temperature shown is for surface mount devices, mounted by vapor phase soldering. throughhole devices (ceramic and plastic dips) can be soldered at +300 c for 10 seconds. ordering guide temperature package package model range description option ad9621an C40 c to +85 c 8-pin plastic dip n-8 ad9621aq C40 c to +85 c 8-pin cerdip q-8 ad9621ar C40 c to +85 c 8-pin soic r-8 ad9621sq C55 c to +125 c 8-pin cerdip q-8 explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. ac testing of a grade devices done on sample basis. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% production tested at +25 c. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature ex- tremes for commercial/industrial devices. ? s 46.5mm ?input 46.5mils cb cb+ ?nput +input +v s output 54mils chip layout theory of operation the ad9621 is a wide bandwidth, unity gain stable voltage feedback amplifier. since its open-loop frequency response fol- lows the conventional 6 db/octave roll-off, its gain bandwidth product is basically constant. increasing its closed-loop gain re- sults in a corresponding decrease in small signal bandwidth. the ad9621 typically maintains a 55 degree unity loop gain phase margin. this high margin minimizes the effects of signal and noise peaking. feedback resistor choice at minimum stable gain (+1), the ad9621 provides optimum dynamic performance with r f @ 51 w . this resistor acts only as a parasitic suppressor against damped r f oscillations that can occur due to lead (input, feedback) inductance and parasitic ca- pacitance. for settling accuracy to 0.1% or less, this resistor should not be required if layout guidelines are closely followed. this value for r f provides the best combination of wide band- width, low parasitic peaking, and fast settling time. when the ad9621 is used in the transimpedance (i-to-v) mode, such as for photo-diode detection, the value for r f and diode capacitance (c i ) are usually known. see figure 1. gener- ally, the value of r f selected will be in the k w range, and a shunt capacitor (c f ) across r f will be required to maintain good am- plifier stability. the value of c f required to maintain < 1 db of peaking can be estimated as: c f @ [(2 w o c i r f - 1) w o 2 r f 2 ] 12 | r f 3 1 k w where w o is equal to the unity gain bandwidth product of the amplifier in rad/sec, and c i is the equivalent total input ca- pacitance at the inverting input. typically w o is 700 10 6 rad/sec (see open loop frequency response curve). as an example, choosing r f of 10 k w and c i of 5 pf, requires c f to be 1.1 pf (note: c i includes both the source and parasitic circuit capacitance). the bandwidth of the amplifier can be esti- mated using the c f calculated as: f 3 db @ 1. 6 2 p r f c f for general voltage gain applications, the amplifier bandwidth can be estimated as: f 3 db @ w o 1 + r f r g ? ? ? ? this estimation loses accuracy for gains approaching +2/C1 or lower due to the amplifiers damping factor. for these low gain cases, the bandwidth will actually extend beyond the cal- culated value. see closed loop bw plots. as a rule of thumb, capacitor c f will not be required if: r f r g () c i ng 4 w o where ng is the noise gain (l + r f /r g ) of the circuit. for most voltage gain applications, this should be the case.
ad9621 rev. 0 C4C phase margin (55 ), low noise current (3.6 pa/ ? hz ), and slew rate (1200 v/ m s) give higher performance capabilities to these applications over previous voltage feedback designs. with a settling time of 11 ns to 0.01% and 7 ns to 0.1%, the de- vice is an excellent choice for dac i/v conversion. the same characteristics, along with low harmonic distortion, make it a good choice for adc buffering/amplification. with its superb linearity at relatively high signal frequencies, it is an ideal driver for adcs up to 14 bits. layout considerations as with all wide bandwidth components, printed circuit layout is critical to obtain best dynamic performance with the ad9621. the ground plane in the area of the amplifier and its associated components should cover as much of the component side of the board as possible (or first interior layer of a multi layer surface mount board). the ground plane should be removed in the area of the inputs and r f and r g to minimize stray capacitance at the input. the same precaution should be used for c b , if used. each power supply trace should be decoupled close to the package with a 0.1 m f ceramic capacitor, plus a 6.8 m f tantalum nearby. all lead lengths for input, output, and feedback resistor should be kept as short as possible. all gain setting resistors should be chosen for low values of parasitic capacitance and inductance, i.e., microwave resistors and/or carbon resistors. microstrip techniques should be used for lead lengths in excess of one inch. sockets should be avoided if at all possible because of their high series inductance. if sockets are necessary, indi- vidual pin sockets such as amp p/n 6-330808-3 should be used. these contribute far less stray reactance than molded socket assemblies. an evaluation board is available from analog devices for a nominal charge. pulse response unlike a traditional voltage feedback amplifier in which slew speed is dictated by its front end dc quiescent current and gain bandwidth product, the ad9621 provides on demand trans- conductance current that increases proportionally to the input step signal amplitude. this results in slew speeds (1200 v/ m s) comparable to wideband current feedback designs. this, com- bined with relatively low input noise current (3.6 pa/ ? hz ), gives the ad9621 the best attributes of both voltage and current feed- back amplifiers. bootstrap capacitor (c b ) in most applications, the c b capacitor will not be required. under certain conditions, it can be used to further enhance set- tling time performance. the c b capacitor (0.001 m f) connects to the internal high im- pedance nodes of the amplifier. using this capacitor will reduce the large signal (4 v) step output settling time by 3 to 5 ns for 0.05% or greater accuracy. for settling accuracy less than 0.05% or for smaller step sizes, its effect will be less apparent. under heavy slew conditions, this capacitor forces the internal signal (initial step) amplitude to be controlled by the on (slewed) transistor, preventing its complement from completely turning off. this allows for faster settling time of these internal nodes and also the output. in the frequency domain, total (high frequency) distortion will be approximately the same with or without c b . typically, the 3rd harmonic will be greater than the 2nd without c b . this will be reversed with c b in place. applications the ad9621 is a voltage feedback amplifier and is well suited for such applications as photo-detector preamp, active filters, and log amplifiers. the devices wide bandwidth (350 mhz), r f c f c i v out figure 1. transimpedance configuration 2 3 4 7 6 0.1 m f 0.1 m f 1 8 6.8 m f r g v in 6.8 m f +v s ? s c b (optional) c f v out r f 500 w a v = 1+ r f r g figure 3. noninverting gain connection diagram 2 3 4 7 6 0.1 m f 0.1 m f 1 8 6.8 m f r f r g r g v in 6.8 m f +v s ? s c b (optional) c f v out r f 500 w a v = ? f r g figure 2. inverting gain connection diagram
ad9621 rev. 0 C5C C typical performance (r l = 100 w ; a v = +1, unless otherwise noted) phase ?degrees open-loop gain ?db 80 60 40 20 0 ?0 0 +15 +30 +45 +60 +75 +90 ?5 ?0 ?5 ?0 frequency ?hz 10k 100k 1m 10m 100m 600m gain phase figure 4. open-loop gain and phase 110 246 204060 frequency ?mhz dbc ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 2nd harmonic r l = 100 w 2nd harmonic r l = 100 w 2nd harmonic r l = 500 w 3rd harmonic r l = 500 w v out = 2v p-p 3rd harmonic r l = 100 w figure 7. harmonic distortion vs. frequency +2 0 ? ? ? ? magnitude ?db phase ?degrees +180 +135 +90 +45 0 ?5 ?0 ?35 ?80 frequency ?mhz 50 100 150 200 250 300 350 400 450 500 r load = 500 w r load = 50 w av = 1 r f = 51 w figure 10. frequency response vs. r load frequency ?hz 10 8 6 4 2 1 10 2 10 3 10 4 10 5 10 6 10 8 6 4 2 1 voltage current noise current ?pa hz noise voltage ?nv/ hz figure 13. input spectral noise density +2 0 ? ? ? ? magnitude ?db phase ?degrees +180 +135 +90 +45 0 ?5 ?0 ?35 ?80 frequency ?mhz 50 100 150 200 250 300 350 400 450 500 a v = ? a v = ? figure 5. inverting frequency response 1 100 10 frequency ?mhz intercept ?+dbm 40 0 20 10 30 50 50 out figure 8. third order intercept +0.1 ?.1 ?.04 ?.08 ?.06 +0.02 ?.02 0 +0.04 +0.06 +0.08 50 040 30 20 10 time ?ns settling percentage v out = 2v step test circuit 100 w 6pf figure 11. short-term settling time supply voltage ? volts 5.5 5.0 4.5 4.0 3.5 output level ? volts 4 3 2 supply current ?ma 27 23 19 voltage current figure 14. output level and supply current vs. supply voltage +2 0 ? ? ? ? magnitude ?db phase ?degrees +180 +135 +90 +45 0 ?5 ?0 ?35 ?80 frequency ?mhz 50 100 150 200 250 300 350 400 450 500 a v = 1 a v = 2 a v = 4 figure 6. noninverting frequency response +20 +45 +70 +25 +30 +35 +40 +50 +55 +60 +65 cmrr 110 1g 10m 1m 100k 10k 1k 100 100m frequency ?hz psrr power supply and common mode rejection ratios ?db figure 9. cmrr and psrr vs. frequency 100k 1 10k 1k 100 10 time ?ns +0.1 ?.1 ?.04 ?.08 ?.06 +0.02 ?.02 0 +0.04 +0.06 +0.08 settling percentage v out = 2v step test circuit 100 w 6pf +2v 0 measuring point figure 12. long-term settling time 0 50 20 10 30 40 30 18 14 22 26 r s ?ohms 10 100 10 1 c load ?pf r s t settling to 0.01% ?ns t settling 51 r s 1k c l figure 15. settling time vs. capacitive load
ad9621 rev. 0 C6C c1721C24C10/92 printed in u.s.a. 0 2v ?v 5ns/div r load = 100 w v out = 5v p-p input rise/fall time = 1.6ns v out ?.2v/div figure 16. large signal pulse response 0 0.2v ?.2v 5ns/div r load = 100 w v out = 0.4v p-p input rise/fall time = 0.3ns v out ?0mv/div figure 17. small signal pulse response 50 10 20 30 40 5 13 noninverting gain settling time ?ns to 0.01% r load = 100 w v out = 2v p-p figure 18. settling time vs. noninverting gain mechanical information dimensions shown in inches and (mm). cerdip (suffix q) 0.015 (0.38) 0.008 (0.20) 0.005 (0.13) min 0.055 (1.4) max 1 pin 1 4 5 8 0.310 (7.87) 0.220 (5.59) 0.405 (10.29) max 0.200 (5.08) max seating plane 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0 to 15 0.320 (8.13) 0.290 (7.37) plastic dip (suffix n) 0.240 (6.096) 0.260 (6.604) 4 5 8 1 seating plane 0.200 (5.08) max 0.360 (9.144) 0.400 (10.16) 0.016 (0.406) 0.020(0.508) 0.045 (1.143) 0.065 (2.667) 0.100 (2.54) bsc 0.290 (7.366) 0.310 (7.874) 0.015 (0.381) 0.008 (0.204) 0.120 (3.048) 0.140 (3.556) 0.140 (3.556) min 0 -15 pin 1 plastic soic (suffix r) top view 0.050 (1.27) typ 0.196 (5.00) 0.188 (4.75) 0.180 (0.46) 0.014 (0.36) 0.069 (1.75) 0.053 (1.35) 0.244 (6.20) 0.228 (5.80) 0.010 (0.25) 0.004 (0.10) 0.045 (1.15) 0.020 (0.50) 0.015 (0.38) 0.007 (0.18) 0.206 (5.20) 0.181 (4.60) 0.158 (4.00) 0.150 (3.80)
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